- Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams
- Slider: an online and active deadlock avoider by serial execution of critical sections
- Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs
- KUMMS: optimising DRAM locality with Kernel-user behaviours
- On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool
15 April 2017
Free sample articles newly available from International Journal of High Performance Systems Architecture
The following sample articles from the International Journal of High Performance Systems Architecture are now available here for free:
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