Special issue: "Emerging Trends in On-Chip Communications"

International Journal of Embedded Systems 5(1/2) 2013

• A highly efficient behavioural model of router for network-on-chip with link aggregation
• Sphere-based topology for networks-on-chip
• Acyclic LBDRe: fault-tolerant routing algorithm for network on chip
• Topologies and routing strategies in MPSoC
• Low power clock gating techniques for synchronous buffer-based queue for 3D MPSoC
• Automated transistor width optimisation algorithms for digital circuits

Additional Papers

• Design of a medium voltage protection device using system simulation approaches: a case study
• Applying partial fault tolerance with explicit area constraints
• Maximising area-constrained partial fault tolerance in reconfigurable logic using selection criteria
• Performance evaluation of platform-specific implementations of numerically complex control designs for nano-positioning applications
• ARTK: a compact real-time kernel for Arduino