Call for papers: "On-Chip Communication: Theory and Applications"

For a special issue of the International Journal of High Performance Systems Architecture.

In a system-on-chip (SoC) design, and particularly in a multi-processor system-on-chip (MPSoC) design, one of the main issues is the interconnection among components, from point-to-point to 3D network-on-chips (NoC). The decision of which kind of interconnection to apply can be based on power consumption, performance, cost and design cycle time. The increasing complexity of applications directly impacts the complexity of on-chip communication, demanding modelling and simulation of new design strategies to optimise design parameters.

For this special issue we invite original research related to on-chip communication theory and its applications. Both theoretical and applied papers on all aspects of design are welcome.

Suitable topics include, but are not limited to, the following:

• Communication-centric design flow
• Bus-based communication architectures
• Current design approaches
• Physical and electrical analysis
• Models for performance exploration
• Power/energy exploration
• Design and synthesis of communication architectures
• Dynamic bus reconfiguration
• Bus encoding techniques
• Interface synthesis and optimisation
• Secure on-chip communication infrastructure
• Custom bus design
• Network-on-chips
• Optical interconnect
• Wireless interconnects
• Physical design trends
• Communication architectures for multi-processor system-on-chips
• On-chip communication in 3D architectures
• Hybrid networks
• Mapping and scheduling tasks
• Reliability and fault-tolerance

Important Dates

Submission of manuscripts: 1 March, 2017
Notification of acceptance: 1 June, 2017
Final version due (tentative): 1 September, 2017